Embedded DRAM built in self test and methodology for test insertion

Abstract

As Application Specific Integrated Circuit (ASIC) technologies expand into new markets, the need for dense embedded memory grows. To accommodate this increased demand, embedded DRAM (eDRAM) macros have been offered in state-of-the-art ASIC library portfolios. [2][3] This integration of eDRAM into ASIC designs has intensified the focus on how best to test a high density macro as complex as Dynamic RAM in a logic test environment. The traditional use of Direct Memory Access (DMA) is costly in silicon area, wiring complexity, and test time. A more attractive solution to this test problem is the use of a Built-In Self Test (BIST) system that is adapted to provide all the necessary elements required for high fault coverage on DRAM, including the calculation of a two-dimensional redundancy solution, pattern programming flexibility, at-speed testing, and test mode application for margin testing.[1][4]. This paper will present an overview of the BIST implemented as part of IBM's third generation eDRAM for the 0.13um ASIC design system. A special emphasis on test pattern integration into the test flow is discussed which describes a developed methodology for taking test patterns from the conceptual stage, through validation, to inclusion in the production test flow.