Designing Multi-Level Resistance States in Graphene Ferroelectric Transistors

Abstract

Conventional memory elements code information in the Boolean “0” and “1” form. Devices that exceed bistability in their resistance are useful as memory for future data storage due to their enhanced memory capacity, and are also a necessity for contemporary applications such as neuromorphic computing. Here, with the aid of an experimentally validated device model, design rules are outlined and more than two stable resistance states in a graphene ferroelectric field-effect transistor are experimentally demonstrated. The design methodology can be extrapolated for on-demand introduction of multiple resistance states in ferroelectric transistors for applications both in data storage and neuromorphic computing.