Electrical modeling of LSCRs in deep submicron CMOS technologies for circuit-level simulation of ESD protection structures

B. Caillard; F. Azaïs; P. Nouet; S. Dournelle; P. Salomé

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Electrical modeling of LSCRs in deep submicron CMOS technologies for circuit-level simulation of ESD protection structures

Proceedings of the IEEE Bipolar/BiCMOS Circuits and Technology Meeting (2003) 97-100

DOI: 10.1109/bipol.2003.1274943

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Abstract

This paper presents an electrical model of a parasitic LSCR that represents the inner currents before and after triggering. It relies on the standard LSCR model before triggering, and on a PIN diode model for the post-triggering behavior. As an illustration, the model has been validated against silicon in both 0.18μm and 0.13μm technologies.

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Caillard, B., Azaïs, F., Nouet, P., Dournelle, S., & Salomé, P. (2003). Electrical modeling of LSCRs in deep submicron CMOS technologies for circuit-level simulation of ESD protection structures. In Proceedings of the IEEE Bipolar/BiCMOS Circuits and Technology Meeting (pp. 97–100). https://doi.org/10.1109/bipol.2003.1274943

Electrical modeling of LSCRs in deep submicron CMOS technologies for circuit-level simulation of ESD protection structures

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