Device scaling in sub-100 nm pentacene field-effect transistors

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Abstract

Reported here is the fabrication of 20-100 nm channel length pentacene field-effect transistors (FETs) with well-behaved current-voltage characteristics. Using a solution deposition method, pentacene grains span entire devices, providing superior contacts. Varying the gate oxide thickness, the effects of scaling on transistor performance is studied. When the channel length to oxide thickness exceeds 5:1, electrostatically well-scaled nanometer FETs are prepared. The results show that the device characteristics are dominated by the contacts. Decreasing the oxide thickness lowers the device turn-on voltage beyond simple field scaling, as sharper bending of the gate potential lines around the contacts more effectively reduces the molecule/source interfacial resistance. © 2006 American Institute of Physics.

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Tulevski, G. S., Nuckolls, C., Afzali, A., Graham, T. O., & Kagan, C. R. (2006). Device scaling in sub-100 nm pentacene field-effect transistors. Applied Physics Letters, 89(18). https://doi.org/10.1063/1.2364154

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