A 6-F2 bit cell design based on one transistor and two uneven magnetic tunnel junctions structure and low power design for MRAM

Abstract

Novel cell structures based on one transistor and two uneven magnetic tunnel junction cell and pillar write word line architecture are proposed to shrink the bit size with a potential down to 6 F2 by a so-called extended via process, and to reduce the writing current by a factor of 2, combined with the nature of nonvolatility and high speed, making the magnetoresistive random access memory suitable for universal memory applications. © 2006 IEEE.