Self-testable CMOS thermopile-based infrared imager

Abstract

This paper describes a CMOS-compatible self-testable uncooled InfraRed (IR) imager that can be used in multiple applications such as overheating detection, night vision, and earth tracking for satellite positioning. The imager consists of an array of thermal pixels that sense an infrared radiation. Each pixel is implemented as a front-side bulk micromachined membrane suspended by four arms, each arm containing a thermopile made of Poly/Al thermocouples. The imager has a pixel self-test function that can be activated off-line in the field for validation and maintenance purposes, with an on-chip test signal generation that requires only slight modifications in the pixel design. The self-test of a pixel takes about 15 ms. The area overhead required by the test electronics does not imply any reduction of the pixel fill factor, since the electronics fits in the pixel silicon boundary. However, the additional self-test circuitry contributes to a small increase in the thermal conductance of a pixel due to the wiring of a heating resistor over the suspended arms. The self-test capability of the imager allows for a production test with a standard test equipment, without the need of special infrared sources and the associated optical equipment. A prototype with 8×8 pixels is currently in fabrication for validation of the self-test approach. In this prototype, each pixel occupies an area of 200×200 μm2, with a membrane size of 90×90 μm2(fill factor of 0.2). Simulation results indicate a pixel thermal conductance of 22.6 μW/K, giving a responsivity of 138 V/W, with a thermocouple Seebeck coefficient that has been measured at 248 μV/K for the 0.6 μm CMOS technology used. The noise equivalent power (considering only Johnson noise in the thermopile) is calculated as 0.18 nW.H-1/2with a detectivity of 5.03×107cm.Hz1/2.W-1, in line with current state-of-the-art. Since the imager may need to measure irradiation intensities below 1μW, with a pixel output voltage much smaller than 1 mV, the analog front-end electronics incorporated on the chip uses modulation and correlated-double-sampling to reduce the amplifier offset and the noise floor.