Low power device design application by magnetic tunnel junctions in Magnetoresistive Random Access Memory (MRAM)

Abstract

The spintronics techniques combines the spin degree and charge which gives rise to state of the art devices like magnetic tunnel junctions which are ultra-low power devices. It is proposed in the paper to evaluate magnetic tunnel junctions (MTJ) at the device level. The paper present an overview of fabrication process, while considering different aspects of the characteristics of MTJs, performance, challenges and a wide range of applications which are different from conventional CMOS technology. The MTJ devices are CMOS compatible for non-volatility, high stability and reliability. The MTJ device is a promising candidate for building non-volatile circuits for ultra- low power operation and fast switching speeds. The current approaches to design logic functionalities and memory devices with MTJs w include hybrid CMOS and MTJ circuits are also discussed in the paper. The results on the most robust magnetic tunnel junction with Resistance Area = 8 Ω-µm2 demonstrates that it satisfies the statistical requirements in parallel with high magnetic tunnel resistance greater than 15σ(Rp), breakdown-of voltage to edge more than 0.5 V, read-induced rate beneath 10−9, and with adequate write endurance, free of undesirable write endurance magnetic inversion. Also this paper demonstrates on the most vigorous MTJ with Resistance Area = 8 Ω-µm2 that satisfies the statistical requirements in parallel with high magnetic tunnel resistance greater than 15σ(Rp),breakdown-of voltage to edge more than 0.5 V, read-induced rate less than 10−9, and with adequate write endurance, and is free of undesirable write endurance magnetic inversion.