Design of spur-free Σ\Δ frequency tuning interface for digitally controlled oscillators

Abstract

Within the framework of a radio-frequency all-digital phase-locked loop, the frequency tuning of a digitally controlled oscillator (DCO) is realized using switchable capacitors (varactors). The minimum feature size and lithographic mismatch of these varactors limit the physical frequency resolution of the DCO to tens of kilohertz. To satisfy the fine frequency resolution of hundreds of hertz in wireless cellular and connectivity standards, high-speed sigma-delta (Σ\Δ) frequency dithering is conventionally employed to improve the time-averaged DCO resolution by at least two orders of magnitude. Unfortunately, the dithering characteristics of the Σ\Δ modulator vary depending on its fractional frequency input and the physical and timing mismatches in the mapping of the multibit digital output to the frequency. This brief investigates the dithering mechanisms that are a potential source of the spurious corruption of the DCO output spectrum and proposes a set of enhancements to mitigate them. Furthermore, the spurious sensitivity to design parameters, such as device mismatch, as well as rise/fall, duty-cycle, and skew timing mismatches, is theoretically analyzed and verified by behavioral simulations.