System-Level Exploration of In-Package Wireless Communication for Multi-Chiplet Platforms

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Abstract

Multi-Chiplet architectures are being increasingly adopted to support the design of very large systems in a single package, facilitating the integration of heterogeneous components and improving manufacturing yield. However, chiplet-based solutions have to cope with limited inter-chiplet routing resources, which complicate the design of the data interconnect and the power delivery network. Emerging in-package wireless technology is a promising strategy to address these challenges, as it allows to implement flexible chiplet interconnects while freeing package resources for power supply connections. To assess the capabilities of such an approach and its impact from a full-system perspective, herein we present an exploration of the performance of in-package wireless communication, based on dedicated extensions to the gem5-X simulator. We consider different Medium Access Control (MAC) protocols, as well as applications with different runtime profiles, showcasing that current in-package wireless solutions are competitive with wired chiplet interconnects. Our results show how in-package wireless solutions can outperform wired alternatives when running artificial intelligence workloads, achieving up to a 2.64× speed-up when running deep neural networks (DNNs) on a chiplet-based system with 16 cores distributed in four clusters.

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APA

Medina, R., Kein, J., Ansaloni, G., Zapater, M., Abadal, S., Alarcón, E., & Atienza, D. (2023). System-Level Exploration of In-Package Wireless Communication for Multi-Chiplet Platforms. In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC (pp. 561–566). Institute of Electrical and Electronics Engineers Inc. https://doi.org/10.1145/3566097.3567952

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