Radix-10 fixed point division hardware

Abstract

Standardization of decimal floating-point formats by IEEE in IEEE 754-2008 Standards fuelled the interest on decimal floating-point architectures among the global research community. Although decimal arithmetic architecture research attracted computer scientists for the last two decades, the major thrust was observed past the year 2008. Multiple proposals have been witnessed for decimal arithmetic units, mostly adders/subtractors, and multipliers. Very few designs have been proposed in the division domain. This article proposes decimal division hardware based on sutras from Vedic Mathematics, the ancient mathematics system. We present a Reduced Magnitude Divisor Generator which converts each digit of the actual divisor into a reduced digit set [-5, 5] using a unique combination/modification of the Vedic Sutras. The divisor digit magnitude reduction also minimizes the product set of multiplication as the single-digit multiplier belongs to the reduced digit set [0, 5] barring the sign. The sign of the dividend or the divisor is not attended during division as a simple XOR operation on the two signs provides the sign of the quotient. Peer comparison has exhibited better results for our design in terms of space and time.