A Programmable Analog Neural Network Chip

Abstract

The parallelism inherent in neural network algorithms is thrown away when they are implemented on digital hardware, resulting in learning that is slow even after careful optimization. A more natural approach is to build real networks with analog VLSI—retaining the parallelism of the algorithm and allowing for some degree of fault tolerance since the circuit may “learn” to compensate for defects. We have fabricated experimental versions of such networks by using MOS capacitors for analog storage of the weights. The incremental weight changes needed for learning are obtained by moving charge between a pair of MOS capacitors on the channel of a transistor connecting them, mimicking a CCD. A 2.5-μm CMOS version has better than 10 bits of dynamic range while using only a 140 ×350- μm2 area to store each weight. A 1.25-μm chip based upon the same cell is capable of peak learning rates of at least 2 ×109 weight changes per second with a 3.5 ×6.0-mm2 die size. ©1989 IEEE