Fast and robust software-based digital phase-locked loop for power electronics applications

Abstract

In this study, a fast and fully software-based algorithm for digital phase-locked loop (PLL) is proposed via a new hybrid approach in software and hardware by using an advanced digital signal processor architecture. The proposed algorithm is robust against line disturbances such as phase-angle jump, voltage sag, third harmonic injection, multi-zero crossing and step change in frequency at the input voltage. Performance and robustness of the proposed method are investigated through experimental studies. Furthermore, it is compared with three different PLL algorithms in detail to show its superiority over existing methods. © The Institution of Engineering and Technology 2013.