Effect of Latitudinal and Longitudinal Grain Boundaries on the Characteristics of Polycrystalline Silicon MOSFET Devices

Abstract

The MOSFETs, Complementary MOS-ICs are the core switch devices of current which also critically affects the ICs. For higher IC performance the present era has shifted to the device scaling to sub-50nm range TFT (thin film transistor) based MOSFET which involves complex fabrication process. The presence of grain boundaries greatly affects the characteristics of these devices. Present paper describes dependence of output characteristics inpolycrystalline silicon MOSFET devices on the longitudinal and latitudinal grain boundaries (GBs) have been investigated theoretically. It is observed that in both latitudinal and longitudinal GBs, the GB scattering potential ‘qφ’ and the GB distribution parameter ‘s’ are equally involved. At all values of gate voltages the contribution in drain current of the device is more due to latitudinal GBs in comparison to longitudinal GBs. However, at high gate voltages longitudinal GBs play a significant role in the drain current of the device.The theoretical computations of the model are synonymous to the experimental work.