Design and Performance Evaluation of D-Flip-Flop using Various Technology Nodes

Abstract

This work focus on design and analysis of various types of Master-Slave D FFs, as sequential circuits are essential for all synchronized circuits we focus on designing and evaluating different D FFs at different technologies. In this work it is observed that Low Power D FF i.e., Proposed D FF has given the better results when compared to the one we studied i.e., master-slave negative edge triggered D FF and the results are as follows, 106% in 22nm technology, 101.4% times better in 45nm technology, 0.8% better in 90nm technology, 5% better in 130nm technology when compared with conventional D FF or Master-Slave Negative Edge Triggered D FF in terms of Propagation Delay. Low Power D FF is 40.37% better in 22nm technology, 87.8% times better in 45nm technology, 92.4% better in 90nm technology, 63.5% better in 130nm technology when compared with conventional D FF or Master-Slave D FF in terms of power dissipation.