Multichip thinning technology with temporary bonding for multichip-to-wafer 3D integration

Abstract

Thinning defects such as chipping and cracking caused by multichip lapping and chemical mechanical polishing processes were evaluated for through-silicon via formation based on via-last/backside via technologies. Two types of temporary adhesives with different Young's moduli were used in this multichip-to-wafer (MC2W) approach for comparison. Impact of the temporary bonding conditions and temporary adhesive properties on the multichip thinning failure was discussed for achieving high-yield MC2W 3D integration. When a temporary adhesive with a low Young's modulus is employed, the space between adjacent chips and the chip sidewall covered with adhesive were found to be critical parameters to the multichip thinning without chipping and cracking.