Energy-efficient sub-DAC merging scheme for variable resolution SAR ADC

Abstract

An energy-efficient capacitive digital-to-analogue converter (DAC) switching method for a reconfigurable successive-approximation register (SAR) analogue-to-digital converter (ADC) is proposed. The proposed method can achieve a variable resolution starting from 1 bit with 1 bit resolution increments. The proposed method achieves the energy savings due to the fact that the binary-weighted capacitors are merged with the main-DAC, as and when required. When sized for the same thermal noise as the traditional SAR ADC, the proposed method achieves 96.9% reduction in switching energy and a factor of 2 improvement in static linearity performance. If sized for the same static linearity as the conventional SAR ADC, the DAC area could be reduced by a factor of 4, which further improves the switching energy savings to 99.2%.