Evaluating AES Security: Correlation Power Analysis Attack Implementation using the Switching Distance Power Model

Abstract

Cryptographic circuits play a critical role in safeguarding confidential information and ensuring secure communication, contributing to the resilience of digital infrastructure under SDG 9 (Industry, Innovation, and Infrastructure). These circuits store encryption keys for the Advanced Encryption Standard (AES) algorithm, including AES-128, AES-192, and AES-256, which are widely used in applications such as online banking and secure messaging platforms. This paper examines the effectiveness of Correlation Power Analysis (CPA), a side-channel attack technique that exploits power consumption patterns in cryptographic circuits, to highlight the challenges of implementing secure encryption systems. The study illustrates the CPA attack procedure against AES implemented on the SASEBO-GII FPGA platform. Experimental results reveal that while the CPA attack based on the Hamming Weight (HW) power consumption model fails to extract the encryption key, the Switching Distance (SD) power consumption model successfully recovers the entire key with a 100% success rate using approximately 4000 power traces. These findings underscore the vulnerability of cryptographic circuits to advanced side-channel attacks and emphasize the need for robust countermeasures to ensure secure data protection, thereby advancing secure and sustainable digital environments under SDG 11 (Sustainable Cities and Communities).