Design a Full Adder Circuit using Modernized Full Sway Exclusive-Or and Exclusive-Nor Gates in 130nm Mentor Graphics

Abstract

In this manuscript, new circuits for XOR/XNOR and concurrent XOR-XNOR purposes are designed. The designed trails are elevated lessened in expressions of the power usage and delay, which are appropriate to low harvest capacitance and low short-circuit power wastage. The designed new hybrid 1-bit full-adder (FA) trails related on the new full sway XOR-XNOR gates. Every designed circuit give their prospective advantages in period of speed, power usage, power delay product (PDP), and dynamic facility and so on. To know the performance of the intended designs, wide-ranging Mentor graphics simulations are carried out. The replications outcomes, supported on the 130-nm CMOS knowledge signify the intended intends have higher rapidity and power over supplementary FA devises. An innovative transistor sizing mode is accessed to reduce the PDP of the tracks. In the designed process, the algebraic working out particle swarm optimization module is utilized to obtain the preferred assessment for finest PDP with less iteration. The designed tracks are checked in times of dissimilarities of the supply, threshold voltages, input noise immunity and size of transistors.