Reducing branch misprediction penalties via dynamic control independence detection

Abstract

This paper presents the concept of dynamic control independence (DCI) and shows how it can be detected and exploited in an out-of-order superscalar processor to reduce the performance penalties of branch mispredictions. We show how DCI can be leveraged during branch misprediction recovery to reduce the number of instructions squashed on a misprediction as well as how it can be used to avoid predicting unpredictable branches by fetching instructions out-of-order. A realistic implementation is described and evaluated using six SPECint95 benchmarks. We show that exploiting DCI during branch misprediction recovery improves performance by 0.9-9.9% on a 4-wide processor, by 1.8-11.2% on an 8-wide processor and by 1.9-15.3% on a 12-wide processor. We also show that using DCI information to fetch instructions out-of-order when an unpredictable branch is encountered potentially improves performance by 0.9-15.2% on a 4-wide processor, by 2.0-14.8% on an 8-wide processor and by 2.6-16.2% on a 12-wide processor. Some of the largest performance gains are observed on go and gcc, which have traditionally posed the most difficult challenge to aggressive branch prediction techniques.