Design of a low jitter multi-phase realigned PLL in submicronic CMOS technology

Abstract

This paper presents a novel PLL and VCO concept based on the multi-phase direct realignment. A multiphase realigned VCO and PLL operating in the 80-240 MHz frequency range have been realized in 0.18μm standard CMOS process, with a 1.8 V power supply voltage. A comparison between realigned and not realigned PLLs showed a jitter improvement by a factor 2 at 240MHz without increasing the power consumption, which is 2.4 mW at 240 MHz. © 2007 IEEE.