Critical dimension and pattern size enhancement using pre-strained lithography

Abstract

This paper proposes a non-wavelength-shortening-related critical dimension and pattern size reduction solution for the integrated circuit industry that entails generating strain on the substrate prior to lithography. Pattern size reduction of up to 49% was achieved regardless of shape, location, and size on the xy plane, and complete theoretical calculations and process steps are described in this paper. This technique can be applied to enhance pattern resolution by employing materials and process parameters already in use and, thus, to enhance the capability of outdated lithography facilities, enabling them to particularly support the manufacturing of flexible electronic devices with polymer substrates.