Stand-by power minimization through simultaneous threshold voltage selection and circuit sizing

Abstract

We present a new approach for estimation and optimization of the average stand-by power dissipation in large MOS digital circuits. To overcome the complexity of state dependence in average leakage estimation, we introduce the concept of `dominant leakage states' and use state probabilities. Our method achieves speed-ups of 3 to 4 orders of magnitude over exhaustive SPICE simulations while maintaining accuracies within 9% of SPICE. This accurate estimation is used in a new sensitivity-based leakage and performance optimization approach for circuits using dual Vt processes. In tests on a variety of industrial circuits, this approach was able to obtain 81-100% of the performance achievable with all low Vt transistors, but with 1/3 to 1/6 the stand-by current.