A K-band power amplifier with adaptive bias in 90-nm CMOS

Abstract

A K-band power amplifier (PA) with adaptive bias circuitry is implemented in 90-nm CMOS technology. The two-stage transformer-coupled differential PA achieves a linear gain of 26.9 dB, a saturation output power (Psat) of 20.4 dBm, an output 1-dB compression point (P1dB) of 18.5 dBm, and a peak power-added-efficiency (PAE) of 17.3% at 21 GHz. With the on-chip adaptive bias control, the bias condition of the amplifier varies dynamically with the input power level, therefore the PAE is optimized. The PAE at P1dB is 13.3%. At the 6-dB back-off power level, the DC power dissipation is reduced by 45% compared to a class-A linear PA.