Design Insights into Thermal Performance of Vertically Stacked JL-NSFET with High-k Gate Dielectric for Sub 5-nm Technology Node

Abstract

This paper demonstrates the impact of temperature variation on vertically stacked junctionless nanosheet field effect transistor (JL-NSFET) concerning analog/RF performances using different gate lengths (L g ) along with high- k gate dielectrics. A comprehensive analysis of analog/RF performances like Transconductance (g m ), Gate capacitance (C gg ), Gate to drain capacitance (C gd ), Output conductance (g ds ), Intrinsic gain (A v ), Maximum oscillation frequency (f MAX ), Gain Frequency Product (GFP), Cutoff frequency (f T ) is carried out for the temperature range 77 K to 400 K. It is noticed that with the decrease in temperature from 400 K to 77 K, there is an improvement in A V , GFP, f T , and f MAX by an amount of ∼7.43%, ∼78.4%, ∼78.38%, ∼50.9% respectively. It is also found A V gets degraded with the downscaling of L g from 16 nm to 8 nm. However, the same resulted in the improvement of RF performance. From detailed analysis, it is further observed that the usage of high- k gate dielectrics ( k = 22) in JL-NSFET devices is not suitable due to the depreciation of analog/RF FOMs. Moreover interestingly, it is also noticed that the improvement in analog/RF performance (ΔFoM=FoM (T=400) − FoM (T=100) ) resulted from lowering the temperature can further be improved by downscaling of L g and by using low- k gate dielectric.