This paper describes the methodology and design of a scalable Montgomery multiplication module. This multiplier can manipulate any number of bits without any limitation. The size of a word depends upon the area which is available and also the performance which is required. After the general architecture is described, hardware organization is analyzed for implementing parallel computation and the discussions on design tradeoffs are done for recognising best configuration for hardware.
CITATION STYLE
Das, S. R., & Sahoo, B. N. (2019). Implementation of montgomery multiplier using scalable architecture. International Journal of Innovative Technology and Exploring Engineering, 8(11 Special Issue), 966–970. https://doi.org/10.35940/ijitee.K1178.09811S19
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