High performance baugh-wooley multiplier using HPM

Abstract

This paper proposes a high speed multiplier designusing VHDL (Very High Speed Integrated Circuits Hardware Description Language). In Booth multiplier multiplication process is done by both encoding and decoding. The Baugh-Wooley algorithm is performing signed multiplication and two’s complement. In both modified Baugh-Wooley and modified Booth recoded multiplier the critical path delay has been reduced by using HPM tree concept and the speed is enhanced. Here the design of 8-bit Modified Baugh-Wooley multiplier and Booth multiplier has been designed and implemented by conventional method and also using High-Performance Multiplier Reduction tree (HPM) method. The speed of Modified HPM Baugh-Wooley operation is increased by appending ripple carry adder. The results are evaluated and synthesized using Xilinx ISE 14.7and Spartan 6 device has been chosen for simulation.