The Research on SAR ADC Integrated Circuit

Abstract

Successive approximation ADCs are widely used in low- and medium-speed applications due to their simpler structure, fewer analog blocks, smaller area, and lower power consumption. The successive approximation ADC mainly includes a sample and hold circuit, a DAC, a comparator, a clock circuit, and a SAR register. The rationality is verified by analyzing, designing and simulating each component circuit. For the research of ADC architecture, SAR type is selected and the key circuit is optimized. Using Cadence layout research, the digital part of ADC circuit can be simulated by Quartus II software and Modelsim software, and the hybrid circuit part is simulated by Candance software PSpice A/D. About layout design, some circuits can be further verified with Proteus software.