A proposal of vertical mosfet and electrothermal analysis for monolithic 3-d ics

Abstract

In this paper, an innovative vertical MOSFET based on through-oxide via (TOV) technology is proposed for silicon-on-insulator (SOI)-based monolithic 3-D ICs. The proposed vertical MOSFET is investigated numerically. It was found that SOI can effectively reduce the parasitic capacitance, leakage current, power consumption, as well as suppress the pulse current interference of the sub-strate. The simulated results indicate that the proposed MOSFET possesses excellent characteristics in saturation current over 1500 µA, sub-threshold swing of 69 mV/dec, and ON/OFF current ratio of 1.28 × 1011 . Moreover, as temperature is a critical factor for the performance degradation of semiconductor devices, electrothermal simulations are conducted to predict the influence of the self-heating effect on device characteristics. The results show that device characteristics slightly deteriorate, but can still acceptable in their applications.