Survey on routing algorithms for fault tolerant in network on chip

Abstract

Latest styles in VLSI study areas archives a variety of cores systems are built-into solitary chip silicon processor in circumstances of submicron gadget. Also these multi main systems are undertaking huge parallel computation process efficiently using Network on Chip architecture. As a router its fundamental duty is to get rid of the whole delay and in addition power dissipation. In this research paper we will explain usuall router strategies and various issues with their operating strategies and propose new ideas for enhancing its efficiency.