Implementation of power optimized binary multiplier based on fast binary counters using symmetric stacking

Abstract

The objective of this work is to introduce a high speed binary counters based on symmetric stacking which is used to design the modified booth multiplier for generation of fast partial products. Using the proposed fast binary counters technique we have devised a strategy for partial product reduction in complex multiplier circuits. By reducing the multiplier partial product complexity, which lead to significant reduction in area and power of the proposed multiplier design.The implementation of 8-bit and 16-bit booth multiplier has been carried out using 90 nm technology in cadence Innovus environment. The Synthesis results states that using proposed fast binary counter technique the area is reduced by 12% and the power is optimized by 8%.