Holistic Die-to-Die Interface Design Methodology for 2.5-D Multichip-Module Systems

Abstract

More than Moore technologies can be supported by system-level diversification enabled by chiplet-based integrated systems within multichip modules (MCMs) and silicon interposer-based 2.5-D systems. The division of large system-on-chip dies into smaller chiplets with different technology nodes specific to the chiplet application requirement enables the performance enhancement at the system level while achieving lower power consumption. However, these chiplets need to communicate with each other. Routing resources in MCM and 2.5-D systems are limited due to system size and thickness restrictions. This work presents an energy/bit optimization approach for multichip systems with the possibility of co-optimization with the routing resources defined by the signaling pitch. Holistic design methodologies are shown which can be further extended by the designer to define the application-specific constraints. A detailed analysis of energy per bit relationship to the voltage swing requirement for different topologies is presented along with a specific CML signaling-oriented design flow for 2.5-D chip-to-chip interfaces as an example of topology-specific optimization possibilities within this methodology.