Delay-Optimistic Multiplier Design using Parallel Prefix Adder with Compressors

Abstract

This article provides an illustration of the design process for 5-2 and 7-2 compressors operating at extremely high speeds. When compared to the prior designs, the new approach significantly reduced the gate-level delay while maintaining an appropriate overall transistor and gate count. With the help of 7:2 and 5:2 compressor infusion, when compared to earlier designs, the gate-level latency has been significantly decreased while the overall transistor and gate counts have remained within acceptable bounds. The technique was created for the 5-2 compressor and expanded for the 7-2 design, which exhibits higher speed performance enhancement for these architectures. To increase performance in terms of latency, we can switch out the ripple carry adder at the last addition for a parallel prefix adder. In addition, careful design considerations were taken to keep other factors, such as power and activity, within reasonable bounds. The best-reported circuits have also undergone redesigns, and the parasitic components of those circuits have been eliminated using the same method to produce a fair comparison. Using a common 16 × 16-bit multiplier, the performance of the built compressor blocks has also been assessed.