Abstract
In this paper we present a BIST method for TSV pre-bond testing. A dedicated test circuitry per TSV is designed and simulated w.r.t a variety of defects and PVT variations. Based on discharge delay evaluation, the BIST scheme supports concurrent testing, requires small-area implementation and it is robust against PVT variations. © 2014 IEEE.
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CITATION STYLE
APA
Di Natale, G., Flottes, M. L., Rouzeyre, B., & Zimouche, H. (2014). Built-in self-test for manufacturing TSV defects before bonding. In Proceedings of the IEEE VLSI Test Symposium. IEEE Computer Society. https://doi.org/10.1109/VTS.2014.6818771
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