Design of Low-Noise CMOS Image Sensor Using a Hybrid-Correlated Multiple Sampling Technique

Abstract

We present a 320 × 240 CMOS image sensor (CIS) using the proposed hybrid-correlated multiple sampling (HMS) technique with an adaptive dual-gain analog-to-digital converter (ADC). The proposed HMS improves the noise characteristics under low illumination by adjusting the ADC gain according to the incident light on the pixels. Depending on whether it is less than or greater than 1/4 of the full output voltage range from pixels, either correlated multiple sampling or conventional-correlated double sampling (CDS) is used with different slopes of the ramping signals. The proposed CIS achieves 11-bit resolution of the ADC using an up-down counter that controls the LSB depending on the ramping signals used. The sensor was fabricated using a 0.11 μm CIS process, and the total chip area was 2.55 mm × 4.3 mm. Compared to the conventional CDS, the measurement results showed that the maximum dark random noise was reduced by 26.7% with the proposed HMS, and the maximum figure of merit was improved by 49.1%. The total power consumption was 5.1 mW at 19 frames per second with analog, pixel, and digital supply voltages of 3.3 V, 3.3 V, and 1.5 V, respectively.