Design of 8T SRAM using FINFET technology

Abstract

Retrieving the data is the major aspect of concern in CMOS technology. At present lower power consumption is the primary objective. The lower power consumption the SRAM cells will be used in the near future extensively. The existing models do not give stability in reading operation because of which a correct logic decision at the output cannot be made. In this paper SRAM cell is designed using FinFET technology and is compared with existing CMOS 45nm technology, and a new SRAM cell structure is proposed which enhances the read stability and write stability with reduction in noise. The transient analysis is done for both CMOS 45nm and FinFET technology based SRAM cell. This proposed model is designed with 8 transistors where 6 transistors are used for data writing and another two are for data reading. The present design increases the read stability.