Timing driven placement using complete path delays

Abstract

A methodology for standard cell or gate array designs is described. A new approach is introduced whereby the placement process is divided into a global step and a detailed step. The timing drive placement (TDP) system balances wirability and timing constraints so that the final released design meets timing criteria. This is achieved by dynamically evaluating the timing of critical paths during placement. TDP is significant because convergence to a timed wirable solution early in the physical design cycle is achieved, or else it becomes apparent that logic changes are required.