Optimal buffering of FPGA interconnect for expected delay optimization

Abstract

The designers of field-programmable gate arrays (FPGAs) always devote to optimize the chip performance. The interconnect delay is a crucial determining factor of circuit performance in FPGA based design. In FPGAs, signals passing through a long wire do not always exit at the end of the wire. Therefore, the expected delay other than end to end delay of the long wire should be optimized. This paper is the first work that addresses expected delay optimization for FPGA interconnect. We present an optimal dynamic programming based approach to insert and size buffers to minimize the expected delay. The experimental results showed that the expected delay of the interconnect buffered with consideration of expected delay optimization sometimes can be significantly smaller than the interconnect buffered for end-to-end delay minimization. © 2007 IEEE.