Technology Mapping for Fpga Using Generalized Functional Decomposition

Abstract

In this paper, we address the technology mapping for RAM-based FPGA. Functional decomposition is applied to decompose a large function into a set of smaller subfunctions such that each subfunction can be implemented using a single logic cell. Our system is mainly divided into two parts. The first part is designed specifically for totally symmetric functions. A Fast-Decompose algorithm based on weight dependency is proposed. The second part deals with general functions. We consider some techniques such as output partition, variable partition, don't care assignment and encoding to minimize the number of subfunctions derived. Using these techniques together, our tool, Fun-Map, improves the mapping results compared with other tools in terms of area and delay. © 1994, Gordon and Breach Science Publishers S.A.