Charge sharing fault detection for CMOS domino logic circuits

Abstract

Because domino logic design offers smaller area and higher speed than conventional CMOS design, it is very popular in high performance processor design. However, domino logic suffers from several design problems and one of the most notable is the charge sharing problem. In domino logic, there are two operations: the pre-charge phase and the evaluation phase. The charge sharing problem occurs when the charge which is stored at the output node in the pre-charge phase is shared among the junction capacitance of transistors in the evaluation phase. Charge sharing may degrade the output voltage level or even cause an erroneous output value. In this paper, we describe a method to measure the sensitivity of the charge sharing problem for a domino gate. For each domino gate, we compute a value called CS-vulnerability which describes the degree of sensitivity for a domino gate to have the charge sharing problem. In addition, our algorithm also generates test vectors to activate the worst case of the charge sharing problem. We have performed experiments on a large set of MCNC benchmark circuits.