Abstract
A model of high-performance computers is derived from instruction timing formulas, with compensation for pipeline and cache memory effects. The model is used to predict the performance of the IBM 370/168 and the Amdahl 470 V/6 on specific programs,and the results are verified by comparison with actual performance. Data collected about program behavior' is combined with the performance analysis to highlight some of the problems with high-performance implementations of such architectures.
Cite
CITATION STYLE
Peuto, B. L., & Shustek, L. J. (1977). An instruction timing model of CPU performance. In Proceedings - International Symposium on Computer Architecture (pp. 165–178). Institute of Electrical and Electronics Engineers Inc. https://doi.org/10.1145/800255.810667
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