Process and Design Challenges for Hybrid Bonding

Abstract

Achieving high-quality interconnect interfaces for fine pitch integration is crucial in today's advanced electronic systems. Among various interconnect options, hybrid bonding stands out as a superior choice due to its ability to accommodate a high input/output (I/O) count, enabling high-density memory integration, increased power delivery, and improved signal speed. To ensure the utmost quality in hybrid bonding, embedding Cu interconnects within the dielectric layer has proven effective. Furthermore, the surface planarization process, accomplished through chemical mechanical polishing (CMP), plays a pivotal role. In this regard, the final CMP process typically involves a meticulous two-step procedure involving copper bulk CMP followed by barrier CMP. The latter yields the desired surface finish crucial for successful hybrid bonding. Several key surface properties, including copper recess (referred to as dishing) in the vias, erosion and roughness of the dielectric layer, and surface topography changes from high-density to low-density copper vias, significantly impact the overall bond yield. To optimize these parameters, a comprehensive understanding of the design of the interconnect layer for the CMP process is essential. In this study, we explore the impact of via scaling and via density for interconnect pitches from 5 μm to 1 μm and the surface topography due to dummy vias of the final bonding surface.