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An adaptive-rate error correction scheme for NAND flash memory

Proceedings of the IEEE VLSI Test Symposium (2009) 53-58
DOI: 10.1109/VTS.2009.24
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Abstract

ECC has been widely used to enhance flash memory endurance and reliability. In this work, we propose an adaptive-rate ECC scheme with BCH codes that is implemented on the flash memory controller. With this scheme, flash memory can trade storage space for higher error correction capability to keep it usable even when there is a high noise level. © 2009 IEEE.

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Chen, T. H., Hsiao, Y. Y., Hsing, Y. T., & Wu, C. W. (2009). An adaptive-rate error correction scheme for NAND flash memory. In Proceedings of the IEEE VLSI Test Symposium (pp. 53–58). https://doi.org/10.1109/VTS.2009.24

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