RD53A: A large scale prototype for HL-LHC silicon pixel detector phase 2 upgrades

Abstract

The Phase 2 upgrades of silicon pixel detectors at HL-LHC experiments feature extreme requirements, such as: 50x50 µm pixels, high rate (3 GHz/cm2), unprecedented radiation levels (1 Grad), high readout speed and serial powering. As a consequence a new readout chip is required. In this framework the RD53 collaboration submitted RD53A, a large scale chip demonstrator designed in 65 nm CMOS technology, integrating a matrix of 400×192 pixels. It features design variations in the analog and digital pixel matrix for testing purposes. An overview of the building blocks will be given together with test results on single chips.