Abstract
Hardware is described for implementing the fast modular multiplication algorithm of P. L. Montgomery. Comparison with previous techniques shows that his method is up to twice as fast as the best currently available, as well as being more suitable for alternative architectures. The gain in speed arises from the faster clock that results from simpler combinational logic. © 1993 IEEE
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APA
Eldridge, S. E., & Walter, C. D. (1993). Hardware Implementation of Montgomery’s Modular Multiplication Algorithm. IEEE Transactions on Computers, 42(6), 693–699. https://doi.org/10.1109/12.277287
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