Value-Aware Error Detection and Correction for SRAM Buffers in Low-Bitwidth, Floating-Point CNN Accelerators

Abstract

Low-power CNN accelerators are a key technique to enable the future artificial intelligence world. Dynamic voltage scaling is an essential low-power strategy, but it is bottlenecked by on-chip SRAM. More specifically, SRAM can exhibit stuck-at (SA) faults at a rate as high as 0.1% when the supply voltage is lowered to, e.g., 0.5 V. Although this issue has been studied in CPU cache design, since their solutions are tailored for CPUs instead of CNN accelerators, they inevitably incur unnecessary design complexity and SRAM capacity overhead. To address the above issue, we conduct simulations and analyses to enable us to propose error detecting and correcting mechanisms that are tailored for our targeting low-bitwidth, floating-point (LBFP) CNN accelerators. We analyze the impacts of SA faults in different SRAM positions, and we also analyze the impacts of different SA types, i.e., stuck-at-one (SA1) and stuck-at-zero (SA0). The analysis results lead us to the error detecting and correcting mechanisms that prioritize fixing SA1 appearing at SRAM positions where the exponent bits of LBFP are stored. The evaluation results show that our proposed mechanisms can help to push the voltage scaling limit down to a voltage level with 0.1% SA faults (e.g., 0.5 V)