The effect of an additional Ti layer in a sub-μm double level Ti/TiN-AlSiCu-TiN metallization for a CMS-LOGIC-process

Abstract

The metallization process for a 0.8/0.6 μm CMS technology for ASIC and LOGIC applications is described. It includes a Ti/TiN barrier for both metal levels, a standard PVD of AlSi(1%)Cu(0.5%) at 350°C, TiN ARC layers and a SOG planarization without etch back. The electromigration resistance for the metal lines, contacts and vias was sufficient, but reliability risks like Si-nodules bigger than half the metal line width, step coverage of contacts and vias depending on aspect ratios of 10 to 50% and unstable via chain resistance (wafer, lot) remained. By introducing a thin Ti wetting layer sputtered in situ immediately before both AlSiCu depositions and by developing a two step AlSiCu PVD process with a high rate/cold sequence followed by a lower rate/hot (470°C) sequence we achieved the following results: Si-nodules were completely eliminated, stabilisation of the step coverage depending on aspect ratio from 30% to completely filled and a tightly distributed via chain resistance. These improvements yielded a double level metallization process for our sub-μm LOGIC and ASIC applications with excellent electromigration performance, fulfilling all MIL standard requirements.