A 112Gb/s PAM-4 Low-Power 9-Tap Sliding-Block DFE in a 7nm FinFET Wireline Receiver

Abstract

Recent advances in ADCs have enabled DSP-based equalization (e.g. extensive FFE and DFE) of wireline channels. FFE and canonical DFE sizes scale linearly with the number of taps, however the computational complexity of an FFE is much greater than that of a DFE. The canonical DFE is challenged by timing closure, and necessary techniques to ease it result in exponential growth in size. As a result, the majority of state-of-the-art DFE implementations have been limited to only 1-2 taps [1-4]. In this paper, a sliding-block DFE (SB-DFE) is introduced that enables pipelining and breaks the barrier to implementing much longer DFEs. Consequently, the DFE length can be extended to encompass all postcursors. Unlike FFEs, DFEs do not amplify noise. Moreover, a long DFE can relax or even remove the postcursor equalization burden on the CTLE and FFE, saving area and power.