Implementing static and dynamic full adders in dynamic body biasing technology

Abstract

In this paper, we proposed the new technology for good performance and high speed. We used dynamic body biasing implemented static and dynamic full adders. This is very useful for threshold voltage decrease by the dynamic body biasing which has good benefit for decrease delay of the circuits. The proposed method provides less power and delay. In Full Adder implementation CMOS technology at 180 nm is used. Simulation is done by cadence virtuoso tool. New static and dynamic Full Adders have been suggested in this paper. We have implemented 8 bit static and dynamic full adder in 180 nm Dynamic Threshold CMOS technology. The proposed DTMOS circuits are faster than existing Full Adder circuits.