The increasing role of polymers in advanced packaging – from stress buffer layers to wafer level underfills and beyond

Abstract

With the continued expansion of computing capability and reduction in technology node for advanced logic or memory devices the challenges encountered due to packaging also increase. Driven by Power, Performance and Area requirements of sub 14nm node devices and their associated system architectures, packaging solutions must also enable optimum performance whilst maintaining an affordable approach, especially within the mobile applications market. Due to this, the role of polymers within the integrated system of multi die packaging becomes ever more important. Polymers have become a vital enabler from both a technical and cost reduction viewpoint, where they have a role to play in various position within the integration scheme. Stress buffers layers are common, but we now move into the era of commercialized wafer level underfills, the use of silicone style materials for Chip Scale Packaging (CSP) to enable more flexible interconnects, Temporary Bonding Materials (TBM) compatible with alternative polymer materials, even pushing to the point of TBM compatibility with overmold materials. Even with all this research the thermal aspects of performance computing means we must also seek improved Thermal Interface Materials (TIMs) in addition to all of the afore mentioned materials.