Efficient finite element method for submicron IC capacitance extraction

Abstract

An accurate and efficient method for extraction of parasitic capacitances in submicron integrated circuits is presented. The method uses a three-dimensional finite-element model in which the conductor charges are approximated by a piecewise linear function on a web of edges located on the surface of the conductors. This yields a system of Green's function integral equations that is solved by a novel approximate matrix inversion technique that only utilizes the entries corresponding to pairs of finite elements that are physically close to each other. With N representing the size of the layout, this results in time and space complexities of O(N) and O(√N), respectively. The method has been implemented in an efficient layout for circuit extraction, and experimental results are presented.